1. Field of the Invention
The present invention relates generally to timing in semiconductor memory devices and, more particularly, to signal sensing and level shifting within semiconductor memory devices.
2. State of the Art
Semiconductor memory devices are used in a myriad of applications. Such memory devices receive data for storage during a write operation and provide stored data to devices or systems external to the memory device during a read operation. Typically, a memory device is accessed through a bus which is controlled by a microprocessor or other digital control mechanism.
As the density of fast memory devices, such as static MOS random access memories (SRAM), increases, it becomes increasingly more difficult to utilize existing memory components. FIG. 1 illustrates a block diagram of an exemplary prior art circuit which includes various componentry utilized in a memory application. FIG. 1 illustrates a memory cell 10 which may be a portion of a generally inclusive memory array of memory cells 10. By way of simplification, the associated timing and control as well as other routing signals associated with a memory array are not depicted in FIG. 1 so as to better isolate the shortcomings of the prior art. Memory cell 10 outputs differential output signals DIN and /DIN to a conventional sense amplifier 12. The sense amplifier depicted in FIG. 1 is typical of a sense amplifier resident on a memory module or system which utilizes lower voltages, illustrated as VCCR, due to the reduced architecture dimensions of memory cell 10. Therefore, sense amplifier 12 receives the data signals and, upon sensing the respective differential relationship of the input signals, generates output signals, illustrated in FIG. 1 as DOUT and /DOUT.
Because the data information retrieved from memory cell 10 is utilized by external devices operating at typically higher voltage levels, the system as illustrated in FIG. 1 further includes a level shifter 14 for receiving the DOUT/DOUT signals from sense amplifier 12 and converting those signals into compatible voltage output signals illustrated as DOUTxe2x80x2 and /DOUTxe2x80x2. In order to perform the level shifting, level shifter 14 is coupled to an external voltage which is generally a higher voltage illustrated in FIG. 1 as VCCX. In order to make the data available to a computing device, a latch 16 retains the data as retrieved from the memory cell and shifted to the higher voltage level for utilization by a processor or other computational device, illustrated in FIG. 1 as processor 18.
While the architecture illustrated in FIG. 1 accomplishes the objective of retrieving data from a memory cell and presenting the data to a processor for consumption, such an architecture does not lend itself to current speeds associated with both the capability of the memory cell as well as the capability of the processor. For example, there is a finite latency associated with the switching of sense amplifier 12. Additionally, level shifter 14 requires a significant amount of time for boosting the signal level. It is not uncommon for memory access times to be on the order of 4 nanoseconds, with separate level shifting alone requiring more than 10% of that time. Accordingly, there exists a need to minimize the overall latency associated with the identification and signal level translation resident within a memory module or system.
In summary, the present invention comprises a sensing and level-shifting apparatus and method for application in a time-sensitive environment where mixed voltage componentry coexists and interoperates. One such environment includes the semiconductor memory realm where high-speed memories with very small signals, and hence low operating power, interoperate with higher-powered computer buses and processors. While sensing the presence of a voltage differential and latching a corresponding output with additional drive capability is presented, the sense amplifier of the present invention further integrates level shifting into the sensing structure and process without the excessive time delays associate with external level shifting.
In one exemplary embodiment of the invention, the level-shifting sense amplifier includes a differential cross-coupled inverter circuit comprised of a pair of inverters that is cross-coupled (i.e., an input of one coupled to the output of the other, and vice versa). The sense amplifier further provides isolation between the lower voltage of the data source (e.g., semiconductor memory) and the higher voltage level-shifting components. Isolation is performed by coupling a pass gate between the input of each inverter and the corresponding one of the differential data inputs of the sense amplifier. The pass gates are controlled by a control signal that isolates the above-described cross-coupled inverters once their gates are charged to the lower or regulated voltage levels.
In order to perform the level-shifting aspects of the invention, the cross-coupled inverters are further coupled to a pull-up circuit in a pull-up arrangement. The pull-up circuit is comprised of at least one pull-up transistor that may couple to one or both of the cross-coupled inverters with the pull-up circuit also being coupled to the higher voltage that is the target voltage for the level-shifting process. In order to complete the circuit, the sense amplifier further includes a pull-down circuit that includes a pull-down transistor coupled to the pair of cross-coupled inverters in a pull-down arrangement. Both the pull-up and pull-down circuits remain in an open-circuit state until the input nodes of the cross-coupled inverters are charged and the pass gates are opened. Upon such an occurrence, both the pull-up and pull-down circuits close and allow the cross-coupled inverters to switch into a latched status with the signal levels being pulled up to the higher level-shifted voltage.
Following the sensing and level-shifting of the input data, residual high voltage remains on the output and input nodes. If the pass gates repeated a subsequent sensing and level-shifting process, the higher voltage would bleed up into memory cells and potentially cause data upset or result in destruction of the memory device. Therefore, the present invention further includes a clamp circuit which is activated following a sensing and level-shifting process. The clamp circuit shorts the differential outputs together and further pulls them up with pull-up transistors to the lower voltage, namely, the voltage levels as utilized on the memory device.
One particular application of the present invention is with respect to SRAM devices where the latency of external level-shifting impairs the desired memory access speed associated with such a technology. The present invention finds application in further integration into memory systems of devices as well as in computer systems or other computational environments that utilize stored data and require sensing of stored data followed by the level-shifting or signal conditioning prior to interconnection with circuitry utilizing higher voltages. Thus, the sense amplifier of the present invention significantly improves memory access times by providing sensing and level-shifting together in one signal transition process. Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.